1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effectively applied to a semiconductor integrated circuit device having a static random access memory (SRAM).
2. Description of the Related Art
For example, in a semiconductor integrated circuit device, characteristic variations (for example, a threshold voltage fluctuation) of transistors are causes of the performance deterioration or malfunction of a semiconductor integrated circuit. In a technique of the semiconductor integrated circuit device, a power supply voltage is lowered with the progress of miniaturization, while the characteristic variations of transistors are increased. Therefore, the influence of the variations has continued to increase. The characteristic variations of transistors cause an operation error of a circuit according to the magnitude of variation. For example, for an SRAM, a noise margin for SRAM operation is reduced according to the magnitude of threshold voltage variation of transistors. As a result, a malfunctioning cell that cannot perform a read operation or a write operation in a normal way is generated. Therefore, the malfunctioning cell is detected by a screening test before shipment of a product, and countermeasures are taken.
As this type of related art, JP-A-2010-182344, for example, discloses a technique of changing the drive voltage of a word line in an operation mode and in a test mode. This is a technique of performing a test in a reduced noise margin state in the test mode, which is aimed at enhancing a detection effect of a defective cell.
Techniques in the related art, including JP-A-2010-182344 described above, are effective for an improvement in test efficiency for the past characteristic variations where the amount of variation is determined at the time of manufacture and thereafter the amount of variation does not change. In the related-art techniques, however, there is a risk of overlooking a malfunctioning cell in which the amount of variation fluctuates with time. This is because, although the cell will be defective due to a large amount of variation, the variation state of a transistor when performing a test operation may happen to be a variation not causing malfunction.
As an example in which the amount of variation temporally changes, there is a phenomenon called random telegraph noise (RTN) whose influence becomes outstanding in the process of miniaturization (refer to FIG. 2 described later). RTN is a phenomenon in which a transistor threshold voltage temporally fluctuates due to a small structural defect at an atomic level. Moreover, the temporal fluctuation has a random characteristic, in the related art, since a temporally fluctuating variation is not tested, a malfunctioning cell can be or cannot be detected depending on a threshold voltage state at the time of a test. Hence, since the cell that will cause malfunction at some future time is overlooked at the test, a design for strengthening a reliability measure such as error correcting code (ECC) is needed. Therefore, there arises a problem in that the degree of redundancy of an SRAM is increased to result in an increase in cost.